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A procedure of designing a self-timed device defined by the model of finite automaton is suggested. In accordance with the chosen automaton standard implementation structure from the automaton transition/output graph one derives the Signal Graph Specification that then is processed by the formal synthesis procedure for self-timed implementation. The design procedure is illustrated by two examples: Stack Memory and Counter with Constant Acknowledge Delay.

V. V. Smolensky, V. I. Varshavsky and V. B. Marakhovsky, "Designing Self-Timed Devices Using the Finite Automaton Model," in IEEE Design & Test of Computers, vol. 12, no. , pp. 14-23, 1995.
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