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Guest Editors' Introduction: More Practical Asynchronous Design

TAM-ANH , Cirrus Logic, Inc.
RABINDRA K. , C&C Research Labs, NEC USA Inc.

Pages: pp. 13-13

It gives us great pleasureto present the final three articles of our special issue on Asynchronous Circuits and Systems. Due to the large number of high-quality articles received and the limited amount of space, we have published these articles serially starting with the Summer 1994 issue of IEEE Design & Test of Computers. These last three articles focus on more theoretical and foundational aspects of asynchronous design.

In "Designing Self-Timed Devices Using the Finite Automaton Model," Victor Varshavsky, Vyacheslav Marakhovsky, and Vadim Smolensky describe a procedure for designing self-timed circuits. They illustrate the effectiveness of their procedure by applying it to the design of a stack memory and constant acknowledgment delay counter.

In "Automatic Verification of Asynchronous Circuits," Trevor Lee, Mark Greenstreet, and Carl-Johan Seger discuss using ordered binary decision diagrams (OBDDs) to provide a rigorous yet practical approach for low-level verification of asynchronous circuits. In one of their examples, their method enabled them to discover an error that went unnoticed during more than 50 hours of CPU simulation time.

Finally, in "High-Level Modeling and Design of Asynchronous Interface Logic," Alexandre V. Yakovlev, Albert Koelmans, and Luciano Lavagno present a formal design methodology, amenable to automation, for realizing interface logic. By dividing the design methodology into two stages—abstract and logic synthesis—they use hierarchical decomposition of the initial design until the logic synthesis algorithms can handle the design's size.


We would like to thankmanaging editor Marie English for her staff's excellent editorial work, Editor-in-Chief Ken Wagner for providing an important forum for presenting some of the latest developments in asynchronous circuits and systems, and the reviewers and contributors to this special issue.

About the Authors

Tam-Anh Chudirects CAD efforts for synthesis and verification of asynchronous and mixed synchronous/asynchronous controllers at Cirrus Logic, Inc., in Fremont, California. Chu received his MS degree in electrical engineering and computer science and his PhD in electrical engineering from MIT.
Rabindra (Rob) K. Royis a research staff member of C&C Research Labs, NEC USA, Inc., in Princeton, New Jersey, where he pursues research in various aspects of testing, synthesis for testability, and low-power design. He received his MS and PhD degrees in electrical engineering from the University of Illinois at Urbana-Champaign.
Direct questions concerning this special topic to Tam-Anh Chu, Cirrus Logic, Inc., 3100 W. Warren Ave., Fremont, CA 94538; or
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