Issue No. 04 - October/December (1994 vol. 11)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.329451
<p>Portable devices demand low power consumption to prolong battery life. Gating the clock is one strategy for saving power. The authors' technique identifies self-loops in an FSM and uses the function described by the self-loops to gate the clock. Applying these techniques to standard benchmarks achieved an average 25% less power dissipation at a cost of only 5% more area.</p>
L. Benini, P. Siegel and G. De Micheli, "Saving Power by Synthesizing Gated Clocks for Sequential Circuits," in IEEE Design & Test of Computers, vol. 11, no. , pp. 32-41, 1994.