Issue No. 02 - April/June (1994 vol. 11)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.282445
<p>TITAC is an asynchronous version of an 8-bit von Neumann microprocessor based on the delay-insensitive model incorporating the isochronic-forks assumption. In its two-phase, event-driven design scheme, a working phase and an idle phase alternate to execute control and data transfer. The data path design uses a two-rail, multilevel AND-OR scheme with a binary decision diagram structure for efficient signal generation.</p>
A. Takamura, T. Nanya, Y. Ueno, H. Kagotani and M. Kuwako, "TITAC: Design of A Quasi-Delay-Insensitive Microprocessor," in IEEE Design & Test of Computers, vol. 11, no. , pp. 50-63, 1994.