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ABSTRACT
<p>To use simulation for design verification, designers need a confidence measure for a given set of simulation patterns, specifically for cases in which only a subset of the possible patterns is used. The authors derive a measure of design verification coverage based on the number of design errors detected in a theoretical analysis of a circuit. To verify the theoretical analysis, they simulate errors and compare the results.</p>
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CITATION
Stephen A. Szygenda, Sungho Kang, "Design Validation: Comparing Theoretical and Empirical Results of Design Error Modeling", IEEE Design & Test of Computers, vol. 11, no. , pp. 18-26, January/March 1994, doi:10.1109/54.262319
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