Issue No. 01 - January/March (1994 vol. 11)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.262318
<p>The authors present ScanBist, a low-overhead, scan-based built-in self-test method, along with its performance in several designs. A novel clock synchronization scheme allows at-speed testing of circuits. This design allows the testing of circuits operating at more than one frequency while retaining the combinational character of the circuit to be analyzed. We can therefore apply scan patterns that will exercise the circuit under test at the system speed, potentially providing a better coverage of delay faults when compared to other self-test methods. Modifications to an existing transition fault simulator account for cases where inputs originating from scan registers clocked at different frequencies drive a gate. We claim to detect transition faults only if the transition originates from the inputs driven by the highest frequency clock. ScanBist is useful at all levels of system packaging assuming that a standard TAP provides the control and boundary scan isolates the circuit from primary inputs and outputs during BIST mode.</p>
D. Burek, B. Nadeau-Dostie and A. S. Hassan, "ScanBist: A Multifrequency Scan-Based BIST Method," in IEEE Design & Test of Computers, vol. 11, no. , pp. 7-17, 1994.