Issue No. 03 - July/September (1993 vol. 10)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.232471
<p>A methodology using a VHDL (VHSIC hardware description language) to create executable models of computer architectures independent of implementation attributes is described. The authors present such a model of a processor architecture known as the WM as the first step in developing an implementation. Simulations using the model can provide performance measurements such as potential parallelism. The model can also serve as an architectural specification for the computer.</p>
J. H. Aylor, M. H. Salinas and B. W. Johnson, "Implementation-Independent Model of an Instruction Set Architecture in VHDL," in IEEE Design & Test of Computers, vol. 10, no. , pp. 42-54, 1993.