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<p>A procedure for estimating the complexity of synthesized designs from finite-state machine (FSM) specifications is described. Incorporating this estimate in the data path synthesis stage allows a trade-off between data path and control logic, resulting in high quality designs in terms of synthesized logic area. It is shown that the estimation process takes 650 to 3000 times less CPU time than the synthesis procedure.</p>
Preeti Panda, Biswadip Mitra, P. Pal Chaudhuri, "Estimating the Complexity of Synthesized Designs from FSM Specifications", IEEE Design & Test of Computers, vol. 10, no. , pp. 30-35, January/March 1993, doi:10.1109/54.199802
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