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Issue No. 04 - October/December (1992 vol. 9)
ISSN: 0740-7475
pp: 40-50
ABSTRACT
<p>X-BLOX, a software tool for mapping architecture-independent designs to field-programmable gate arrays (FPGAs), is described. X-BLOX synthesizes a delay- and area-efficient logic-level design from an input specification consisting of a network of generic modules. The tool automatically propagates partial data type specification, performs architecture-specific design optimization, and performs context-dependent module synthesis.</p>
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CITATION

J. P. Seidel and S. H. Kelem, "Shortening the Design Cycle for Programmable Logic," in IEEE Design & Test of Computers, vol. 9, no. , pp. 40-50, 1992.
doi:10.1109/54.173332
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