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<p>A method for automatic multipartitioning of a multiple-output logic function into the smallest number of subfunctions for mapping to fixed-size PLAs of a field-programmable gate array (FPGA) chip is described. A detailed example to demonstrate the procedure is presented. It is shown that, for this example, the method produced almost optimum partitions in a fast and efficient manner.</p>
Maciej Ciesielski, David Harrison, Zafar Hasan, "A Fast Partitioning Method for PLA-Based FPGAs", IEEE Design & Test of Computers, vol. 9, no. , pp. 34-39, October/December 1992, doi:10.1109/54.173331
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