Issue No. 04 - October/December (1992 vol. 9)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.173329
<p>A delay fault diagnosis process consisting of simulation of the fault-free circuit with a four-valued logic algebra and critical-path tracing from primary outputs to primary inputs is presented. An alternative to fault simulation, the method requires no delay-size-based fault models and considers only the fault-free circuit. A sensitivity analysis process for improving diagnosis accuracy is also presented.</p>
S. Pravossoudovitch, P. Girard and C. Landrault, "Delay-Fault Diagnosis by Critical-Path Tracing," in IEEE Design & Test of Computers, vol. 9, no. , pp. 27-32, 1992.