Issue No. 04 - October/December (1992 vol. 9)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.173328
<p>A signature generation algorithm for linear-feedback shift register (LFSR)-based compactors used in fault simulation of built-in self-test digital circuits is presented. The algorithm uses small- to medium-size lookup tables to generate signatures for internal as well as external exclusive-OR LFSRs of any length. The basic concept can be extended to general linear compactors. Algorithms that convert signatures from one form of LFSR to the other are also presented.</p>
K. K. Saluja and C. See, "An Efficient Signature Computation Method," in IEEE Design & Test of Computers, vol. 9, no. , pp. 22-26, 1992.