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Issue No. 01 - January/March (1991 vol. 8)
ISSN: 0740-7475
pp: 21-34
<p>A two-value, zero-delay simulator that computes signatures and analyzes fault coverage for circuits with built-in self-test (BIST) is described. The simulator, called the compiled logic simulator (CLS), is used with a monitor that simulates BIST control logic at a high level. The simulator's compiled code is well suited to the IBM 3090 pipeline and fault simulation using flat random patterns. The linear-feedback-shift-register simulation monitor is discussed. Performance results are presented. Fault simulation with one million random patterns on a 40000-gate circuit was done in 16 CPU minutes.</p>

B. Keller, D. P. Carlson and W. Maloney, "The Compiled Logic Simulator," in IEEE Design & Test of Computers, vol. 8, no. , pp. 21-34, 1991.
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