Issue No. 04 - July/August (1990 vol. 7)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.57906
<p>The design verification of the cache controller for SPUR, a shared-memory multiprocessor, is reported. The strategy was to develop a random tester that would generate and verify the complex interactions between multiple processors in functional simulation. Replacing the CPU model, the tester generates memory references by random selection from a script of actions and checks. It was easy to develop and detect over half the bugs uncovered during functional simulation. A prototype SPUR multiprocessor system that runs the Sprite operating system is being used for experiments in parallel programming. Results to data are described.</p>
R. H. Katz, D. A. Wood and G. A. Gibson, "Verifying a Multiprocessor Cache Controller Using Random Test Generation," in IEEE Design & Test of Computers, vol. 7, no. , pp. 13-25, 1990.