Issue No. 03 - May/June (1990 vol. 7)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.56465
<p>An approach to switch modeling that provides an excellent compromise between accuracy and performance and requires only minor modifications to basic gate-level simulators is described. The evaluation technique is fully compatible with the VHDL (VHSIC hardware description language) specification. Switch and node models are implemented as primitive elements to achieve maximum performance, but models could also be implemented entirely in VHDL source code. MCC has successfully run the VHDL system based on this approach on a variety of test circuits, and it is now in general release. The model and its integration with a VHDL simulator are discussed, a design example is presented, and some refinements to the switch model are described.</p>
S. P. Smith and R. D. Acosta, "A Value System for Switch-Level Modeling," in IEEE Design & Test of Computers, vol. 7, no. , pp. 33-41, 1990.