Issue No. 02 - March/April (1990 vol. 7)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.53042
<p>The evolution of a testing method and architecture of a logic-device tester to be used for the next generation of IBM's high-density CMOS ASIC (application-specific integrated circuit) logic components is described. The tester's design is based on the architecture of an existing IBM memory tester rather than on a conventional logic-tester design. The testing strategy calls for boundary-scan in each component design, built-in self-test logic within embedded memory arrays, and the use of weighted random-pattern logic testing. The development of the tester hardware is discussed, and capital costs of the new tester are compared with those of other approaches.</p>
R. W. Bassett et al., "Low-Cost Testing of High-Density Logic Components," in IEEE Design & Test of Computers, vol. 7, no. , pp. 15-28, 1990.