Issue No. 06 - November/December (1989 vol. 6)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.41671
<p>Synthesis algorithms that offer a technique for scheduling operations and allocating registers and buses in light of both timing constraints and available hardware resources are presented. They enhance current scheduling techniques by using a global priority function that minimizes storage, interconnections, and functional unit cost. Algorithms for allocating registers and buses minimize storage and interconnection costs and take into account the interdependence of both tasks. The algorithms are also applicable to more than one method of synthesis; although first implemented in the HAL system, they have since been integrated into more specialized high-level synthesis systems.</p>
J. P. Knight and P. G. Paulin, "Algorithms for High-Level Synthesis," in IEEE Design & Test of Computers, vol. 6, no. , pp. 18-31, 1989.