Issue No. 04 - July/August (1989 vol. 6)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.32421
<p>The authors describe a method for diagnosing the failures observed in testing VLSI designs that use the scan-path structure. Diagnosis consists of simulating selected faults after testing using a fault simulator that allows the application of several patterns in parallel. The method is also suitable for signature-based random-pattern testing. The authors discuss diagnostic fault simulation, fault-list generation, relating faults to defects, diagnostic strategy, and random-pattern failures, and they report some experimental results to indicate the procedure's power.</p>
E. Lindbloom and J. Waicukauski, "Failure Diagnosis of Structured VLSI," in IEEE Design & Test of Computers, vol. 6, no. , pp. 49-60, 1989.