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Issue No. 04 - July/August (1989 vol. 6)
ISSN: 0740-7475
pp: 32-48
<p>The author presents an architecture for implementing scan technology in a state-of-the-art workstation that uses a single resource to control scan and clock functions and perform pseudorandom testing of individual chips and boards. The testing approach, which is based on the use of a linear-feedback shift register, also features the ability to capture test results and compress them into a single signature for comparison with a known 'golden-circuit' signature. The author describes an application for testing the Apollo DN10000 and presents a list of design rules for pseudorandom testing at the board level. He discusses communication with scan and clock resources, timing relationships for scan operations, problems encountered, and design-for-testability issues in some depth.</p>

B. I. Dervisoglu, "Scan-Path Architecture for Pseudorandom Testing," in IEEE Design & Test of Computers, vol. 6, no. , pp. 32-48, 1989.
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