Issue No. 03 - May/June (1989 vol. 6)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.32410
<p>The techniques that researchers have used to control error in VLSI placement are surveyed. The author discusses the application of parallelism, synchronization with serial subsets, combining algorithms, periodic synchronization, shared-memory implementation, local-memory implementation, and connection Machine implementation. The issues of temporary versus cumulative error, task allocation, and error measurements are examined.</p>
M. Durand, "Parallel Simulated Annealing: Accuracy vs. Speed in Placement," in IEEE Design & Test of Computers, vol. 6, no. , pp. 8-34, 1989.