Issue No. 02 - March/April (1989 vol. 6)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.19132
<p>The authors present a method for fully testing chips designed using synthesis and silicon compilation. The method is targeted for a multiprocessor architecture that implements low-speed to medium-speed signal-processing algorithms. By taking advantage of the specific properties of the architecture, the method allows a chip to be partitioned into several functional units. The authors use the C-test concept instead of the traditional automatic test-pattern generation to derive a compact set of test vectors. The fault model covers both the stuck-at class and part of the transistor stuck-open and stuck-closed cases. For large units with embedded memory, the authors adopt a self-test approach.</p>
"A Testability Strategy for Microprocessor Architecture," in IEEE Design & Test of Computers, vol. 6, no. , pp. 18-34, 1989.