Issue No. 01 - January/February (1989 vol. 6)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.20387
<p>The authors present the specification and design of a self-test mechanism for static random-access memories (RAMs). The test algorithm provides excellent fault detection, and its structure is independent of address and data scrambling. The self-test machine generates data backgrounds on chip and is therefore suitable for both bit-oriented and word-oriented SRAMs. It is also suitable for both embedded SRAMs and stand-alone SRAMs, and adapts to boundary-scan environment. Because of the regular and symmetric structure of the test algorithm, the silicon overhead is only 3% for a 16 K synchronous SRAM.</p>
L. Thijssen, R. Dekker and F. Beenker, "Realistic Built-In Self-Test for Static RAMs," in IEEE Design & Test of Computers, vol. 6, no. , pp. 26-34, 1989.