Issue No. 06 - November/December (1988 vol. 5)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.9271
<p>An efficient method is proposed for placing modules in large and highly complex sea-of-gates chips that include preplaced I/O pads and macrocells. PROUD repeatedly solves sparse linear equations. A resistive network analogy of the placement problem and convexity of the objective function are key concepts in this algorithm. The algorithm was tested on nine real circuits. For a triple-metal-layer, 100000-gate sea-of-gate design with 26000 instances, the constructive phase took 50 minutes on a VAX 8650 and yielded excellent results for total wire length. Extensions of the method are considered.</p>
E. S. Kuh, R. Tsay and C. Hsu, "PROUD: A Sea-Of-Gates Placement Algorithm," in IEEE Design & Test of Computers, vol. 5, no. , pp. 44-56, 1988.