Issue No. 06 - November/December (1988 vol. 5)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.9270
<p>An algorithm is presented for extracting a two-level subnetwork hierarchy from flat netlists. They discuss the application of this algorithm to incremental circuit analysis in the Cosmos compiled switch-level simulator. The algorithm decreases the network preprocessing time for Cosmos by nearly an order of magnitude. The file system is used as a large hash table that retains information over many executions of the incremental analyzer. The hierarchy-extraction algorithm computes a hash signature for each subnetwork by coloring vertices somewhat the way wirelist-comparison programs do. It then identifies duplicates, using standard hash-table techniques.</p>
D. L. Beatty and R. E. Bryant, "Incremental Switch-Level Analysis," in IEEE Design & Test of Computers, vol. 5, no. , pp. 33-42, 1988.