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Issue No. 05 - September/October (1988 vol. 5)
ISSN: 0740-7475
pp: 28-40
ABSTRACT
<p>Presents a novel approach for automating the timing design of interfaces between VLSI chips in microcomputer systems. The Prolog-based expert system, called TDS (for timing design system), incorporates the heuristic knowledge of the hardware designer. TDS is a rule-based system that interprets the specification sheets of VLSI chips and can synthesize, diagnose, and verify timing charts at the expert's level. The system uses a functional model based on timing specifications, not the structural information. TDS can model other interfaces that are based on timing specifications, such as standard bus interfaces.</p>
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CITATION
Ravi Rastogi, Kazuhiko Kawamura, Atsushi Kara, "An Expert System to Automate Timing Design", IEEE Design & Test of Computers, vol. 5, no. , pp. 28-40, September/October 1988, doi:10.1109/54.7980
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