Issue No. 04 - July/August (1988 vol. 5)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.7967
<p>A built-in test structure is described that is based on the ATS algorithmic test sequence, which provides the shortest possible test for stuck-at faults in a random-access memory (RAM). An initialization step has been added to ATS that allows the modified procedure to detect bit-rail faults. In the test mode, the memory address register is converted to a count-by-three circuit controlled by a four-latch test sequencer. A simple data-compare circuit is placed on the RAM outputs to detect faults.</p>
W. H. McAnney and P. H. Bardell Jr., "Built-In Test for RAMs," in IEEE Design & Test of Computers, vol. 5, no. , pp. 29-36, 1988.