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Issue No. 03 - May/June (1988 vol. 5)
ISSN: 0740-7475
pp: 56-63
ABSTRACT
<p>Parallel testing of memories at the wafer-sort stage can offer significant throughput advantages. Accepted methods at this state involve synchronous prober control. A model is presented that shows how asynchronous prober control can increase throughput 36% over that possible with synchronous control.</p>
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CITATION
Robert J. Powers, "Throughput Advantages of Asynchronous Prober Control", IEEE Design & Test of Computers, vol. 5, no. , pp. 56-63, May/June 1988, doi:10.1109/54.7963
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