Issue No. 03 - May/June (1988 vol. 5)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.7963
<p>Parallel testing of memories at the wafer-sort stage can offer significant throughput advantages. Accepted methods at this state involve synchronous prober control. A model is presented that shows how asynchronous prober control can increase throughput 36% over that possible with synchronous control.</p>
R. J. Powers, "Throughput Advantages of Asynchronous Prober Control," in IEEE Design & Test of Computers, vol. 5, no. , pp. 56-63, 1988.