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Issue No. 04 - July/August (1987 vol. 4)
ISSN: 0740-7475
pp: 42-49
Dick Liu , Stanford University
Edward McCluskey , Stanford University
Conventional testing techniques often fail to be effective for CMOS combinational circuits, since most of their switch-levelfaults cannot be detected by stuck-at-fault testing. The alternative is to design for testability. The design techniques presentedhere for fully testable CMOS combinational circuits use a three-pattern test scheme to detect both stuck-open and stuck-onswitch-level faults. The circuit is implemented with specially designed gates that have no undetectable stuck-on faults. Aninverting buffer is inserted between logic gates, and two FETs are added to each logic gate to make it testable for stuck-onfaults.

D. Liu and E. McCluskey, "Designing CMOS Circuits for Switch-Level Testability," in IEEE Design & Test of Computers, vol. 4, no. , pp. 42-49, 1987.
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