Issue No. 04 - July/August (1987 vol. 4)
Randal Bryant , Carnegie Mellon University
The switch-level model provides a logical abstraction from the physical structure of a metal-oxide semiconductor(MOS) circuitto its digital behavior. At the switch level, a circuit is modeled as a network of transistor switches connecting a set ofcharge storage nodes. Node voltages are represented by discrete logic levels, and electrical behavior is modeled in a highlysimplified way. Switch-level algorithms have been applied to such tasks as logic and fault simulation, formal hardware verification,timing analysis, and automatic test program generation. They have been implemented on sequential and parallel computers aswell as by hardware simulation accelerators.
R. Bryant, "A Survey of Switch-Level Algorithms," in IEEE Design & Test of Computers, vol. 4, no. , pp. 26-40, 1987.