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Issue No. 01 - January/February (1987 vol. 4)
ISSN: 0740-7475
pp: 24-31
W. Fuchs , University of Illinois
Sy-yen Kuo , University of Illinois
Yield degradation from physical failures in large memories and processor arrays is of significant concern to semiconductormanufacturers. One method of increasing the yield for iterated arrays of memory cells or processing elements is to incorporatespare rows and columns in the die or wafer. These spare rows and columns can then be programmed into the array. The authorsdiscuss the use of CAD approaches to reconfigure such arrays. The complexity of optimal reconfiguration is shown to be NP-complete.The authors present two algorithms for spare allocation that are based on graph-theoretic analysis. The first uses a branch-and-boundapproach with early screening based on bipartite graph matching. The second is an efficient polynomial time-approximationalgorithm. In contrast to existing greedy and exhaustive search algorithms, these algorithms provide highly efficient andflexible reconfiguration analysis.
W. Fuchs, Sy-yen Kuo, "Efficient Spare Allocation for Reconfigurable Arrays", IEEE Design & Test of Computers, vol. 4, no. , pp. 24-31, January/February 1987, doi:10.1109/MDT.1987.295111
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