Issue No. 04 - July/August (1986 vol. 3)
Thirumalai Sridhar , Texas Instruments
Memory test times?and thus test costs?are increasing rapidly as the size of the memories grows each year. Testability techniquestherefore must be developed to reduce the test time without compromising the test quality. This article presents an approachthat meets this goal using parallel signature analyzers (PSAs). PSAs can access more data cells in parallel than I/O pinscan, and the approach's parallelism reduces the test time. The proposed method is analyzed with respect to test time, testquality, and silicon area penalty.
T. Sridhar, "A New Parallel Test Approach for Large Memories," in IEEE Design & Test of Computers, vol. 3, no. , pp. 15-22, 1986.