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Issue No.03 - May/June (1986 vol.3)
pp: 52-56
Dilip Bhavsar , Digital Equipment Corporation
A New implementation for scannable flip-flops in MOS is economical for use in systems that use single latch design. The ?SystemLatch-Scannable Flop? (SL-SF) requires two additional transfer gates, two test clocks, and possibly a test mode signal. Hardwarepernalties paid in SL-SF can be the least among other implementations with equivalent test functionality. This article discussesSL-SF only in the context of its scan-path implementation; its applicability to linear feedback shift-register-based self-testshould be obvious.
Dilip Bhavsar, "A New Economical Implementation for Scannable Flip-Flops in MOS", IEEE Design & Test of Computers, vol.3, no. 3, pp. 52-56, May/June 1986, doi:10.1109/MDT.1986.294994
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