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Issue No. 03 - May/June (1986 vol. 3)
ISSN: 0740-7475
pp: 46-51
K.L. Kodandapani , Digital Equipment Corporation
Edward McGrath , Digital Equipment Corporation
ABSTRACT
We will describe a wirelist compare program that, together with a VLSI node extractor, is used to verify VLSI IC layout connectivity.Engineers at Digital Equipment Corporation have successfully used this tool in a production environment to debug layout errors.The program is based on a graph isomorphism algorithm and provides graphical and textual guides to pinpoint errors. We willexamine this algorithm, its error outputs, and provide run-time statistics.
INDEX TERMS
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CITATION

E. McGrath and K. Kodandapani, "A Wirelist Compare Program for Verifying VLSI Layouts," in IEEE Design & Test of Computers, vol. 3, no. , pp. 46-51, 1986.
doi:10.1109/MDT.1986.294992
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