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Issue No. 05 - September/October (1985 vol. 2)
ISSN: 0740-7475
pp: 61-73
Nobuhiko Koike , NEC Corporation
Kenji Ohmori , NEC Corporation
Tohru Sasaki , NEC Corporation
ABSTRACT
The architecture of a very-high-speed logic simulation machine (HAL), which can simulate up to one-half million gates and2M-byte memory chips at a 5 ms clock speed, is described. This machine makes it possible to debug the total system?CPU, mainmemory, cache memory and control storage?before the actual machine is fabricated. HAL employs parallel and pipeline processing,and event-driven, block-level logic simulation. The prototype system for a 32-processor system has been constructed and isnow in use as a tool for large mainframe computer development. HAL is more than a thousand times faster than existing softwarelogic simulators.
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CITATION

N. Koike, T. Sasaki and K. Ohmori, "HAL: A High-Speed Logic Simulation Machine," in IEEE Design & Test of Computers, vol. 2, no. , pp. 61-73, 1985.
doi:10.1109/MDT.1985.294819
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