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Issue No. 05 - September/October (1985 vol. 2)
ISSN: 0740-7475
pp: 54-60
Shigehiro Funatsu , NEC Corporation
Masato Kawai , NEC Corporation
ABSTRACT
A new test-generation system (FUTURE) for large digital circuits (more than 10K gates) is based on a nine-valued FAN algorithm.Fault simulation adopts a concurrent simulation adopts a concurrent simulation technique. The system consists of four majormodules: fault modeling, random pattern generation, algorithmic pattern generation, and fault simulation. The system can bea powerful CAD tool and effectively generate test patterns for large sequential circuits with Scan Path.
INDEX TERMS
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CITATION

M. Kawai and S. Funatsu, "An Automatic Test-Generation System for Large Digital Circuits," in IEEE Design & Test of Computers, vol. 2, no. , pp. 54-60, 1985.
doi:10.1109/MDT.1985.294817
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