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Issue No. 05 - September/October (1985 vol. 2)
ISSN: 0740-7475
pp: 43-53
Tokinori Kozawa , Hitachi Central Research Laboratory
Hidekazu Terai , Hitachi Central Research Laboratory
Since Japanese R&D efforts began in the late 1960s, advances in LSI circuit design automation have made possible the designof custom logic VLSI circuits with up to 10,000 gates. Automatic placement and routing programs have become essential DA toolsin both master-slice LSI circuit design, and the custom design of VLSI circuits with up to 100,000 gates. Algorithms for VLSIDA systems include automatic floor planning, automatic cell placement, and automatic routing. Hierarchical design is an efficientapproach to the layour of huge numbers of transistors; a VLSI circuit with 74,000 transistors and 17,000 gates was designedusing such an approach. The layout design effort required less than 10 man-months, and the chip was fabricated with no erroron the first design.
Tokinori Kozawa, Hidekazu Terai, "Research in Design Automation for VLSI Layout", IEEE Design & Test of Computers, vol. 2, no. , pp. 43-53, September/October 1985, doi:10.1109/MDT.1985.294816
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