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Issue No. 04 - July/August (1985 vol. 2)
ISSN: 0740-7475
pp: 56-68
Magdy Abadir , University of Southern California
Melvin Breuer , University of Southern California
The complexity of VLSI circuits has increased the need for design for testability (DFT). Numerous techniques for designingmore easily tested circuits have evolved over the years, with particular emphasis on built-in testing approaches. What hasnot evolved is a design methodology for evaluating and making choices among the numerous existing approaches. This articledescribes efforts to build a knowledge-based expert system for designing testable VLSI chips. A framework for a methodologyincorporating structural, behavioral, qualitative, and quantitative aspects of known DFT techniques is introduced. This methodologyprovides a designer with a systematic DFT synthesis approach. The process of partitioning a design into subcircuits for individualprocessing is described and a new concept?I-path?is used to transfer data from one place in the circult to another. Rulesfor applying testable design methodologies to circuit partitions and for evaluating the various solutions obtained are alsopresented. Finally, a case study using a prototype system is described.

M. Breuer and M. Abadir, "A Knowledge-Based System for Designing Testable VLSI Chips," in IEEE Design & Test of Computers, vol. 2, no. , pp. 56-68, 1985.
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