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Issue No. 09 - Sept. (2016 vol. 49)
ISSN: 0018-9162
pp: 69-77
Lui Sha , University of Illinois at Urbana-Champaign
Marco Caccamo , University of Illinois at Urbana-Champaign
Renato Mancuso , University of Illinois at Urbana-Champaign
Jung-Eun Kim , University of Illinois at Urbana-Champaign
Man-Ki Yoon , University of Illinois at Urbana-Champaign
Rodolfo Pellizzoni , University of Waterloo
Heechul Yun , University of Kansas
Russell B. Kegley , Lockheed Martin
Dennis R. Perlman , Lockheed Martin
Greg Arundale , Rockwell Collins
Richard Bradford , Rockwell Collins
ABSTRACT
Architects of multicore chips for avionics must define and bound intercore interference, which requires assuming a constant worst-case execution time for tasks executing on the chip. With the Single Core Equivalent technology package, engineers can treat each core as if it were a single-core chip.
INDEX TERMS
real-time systems, multicore architecture, multicore chips, memory-access conflicts, multicore processing, avionics computing, single-core equivalence
CITATION
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