The Community for Technology Leaders

32 & 16 Years Ago

Pages: pp. 20-21


ISSUE INTRODUCTION (p. 8) “Today’s array processors provide a cost-effective tool for increasing the speed at which highly computation-bound processing jobs can be carried out. They are maturing and expanding with greatly improved hardware and software—improvements that are primarily a result of the accumulated experience of the vendors and users of these machines. All in all, it is a very competitive environment.”

PERIPHERY (p. 11) “In recent years, peripheral array processing has become so pervasive that it has assumed the trappings of an autonomous discipline. It is our purpose here to provide a perspective on the hardware and software issues of this emerging field.”

INTENSE COMPUTATION (p. 18) “The design objective of the FPS-AP family is to efficiently perform the computationally intensive portions of scientific and signal processing. The architectural challenge was to devise arithmetic elements, memories, and registers that could be programmed effectively and manufactured at a reasonable cost.”

ASYNCHRONICITY (p. 28) “Modern array processors can give more floating-point calculations per dollar than conventional computers by the efficient use of parallel equipment. At the same time, they conform quite well to programmability characteristics found in conventional computers. This article describes the general design philosophy and some architectural features of the CSPI MAP-200, a modern array processor that achieves these desirable characteristics by using asynchronous functional parallelism.”

INTEGRATION (p. 41) “There are many elements to be considered in the integration of an array processor into a scientific computing environment. Our intention here is to clarify these elements and their relationships through detailed discussions of compatibility considerations, host supervisory software operating overhead, and an example system.”

PRECOMPILATION (p. 48) “It is an accepted fact that attached array processors have an impressive cost/performance ratio. On the surface, adding one to a host computer appears to offer an inexpensive approach to acquiring additional computing power, but the difficulties involved in converting programs to make efficient use of array processors have limited their application to a relatively few areas. … This situation is now changing.”

BIBLIOGRAPHY (p.53) “… includes most of the trade journal articles, conference papers, and technical reports on array processors published in the English language since 1975.”

DATA STRUCTURE (p. 60) “Our objective is not to define an architecture … but to further consider the problems that have to be solved in attaining an eventual structure, satisfactory to its users, for processing and communicating all kinds of information. The ideas resulting from this study—for instance, a method for measuring the quality of information—may guide the design of new systems and provide methods for evaluating alternative approaches.”

TUTORIAL (p. 77) “Providing complex functions in systems that can be easily used by those with limited skills and training is the major challenge facing small business system designers.”

CHARTING FLOW (p. 96) “What is required … is a very high-level ‘reverse’ language which, using the source code as input, would generate a flowchart of the program, validity limits, and typing of all variables accompanied by a putative problem statement for the program (or module).”

POCKET PRINTING (p. 109) “Tandy Corporation has introduced a combined printer/cassette interface unit for its Radio Shack TRS-80 pocket computer.”

MASS STORAGE (p. 112) “Utilizing Winchester technology, five field-upgradable models of a mass storage subsystem for the financial and banking industries have been introduced by Honeywell. Collectively called the CDS7000, the 8" drives consist of Winchester-type fixed, rigid disks as well as removable diskettes. These devices may be configured alone or in combination, offering formatted storage capacities ranging from 630K to 8.7M bytes.”

DISK INSPECTION (p. 120) “… the Automatic Eddy Current machine is under development for inspection of compressor and turbine disks and other circular engine parts removed from service. It is designed to do disk inspections faster and more reliably than current semiautomatic machines or manual inspection techniques.”


WRITE ONLY (p. 8) “We should just admit that technology has reached a level where all entities using a communication channel (such as a bus) can be economically made sophisticated enough to DMA. Programming of the DMA then simply becomes part of the communication protocol and can be made very efficient. By allowing the programmer access to the protocol as well, the entire system is better utilized. The communication protocol can then be simplified by realizing that if all entities on the bus are capable of writing, reading is unnecessary. And writes are easy!”

SHORT CYCLING (p. 12) “Many companies have tried to gain a competitive advantage in the marketplace by shortening their development cycles and rushing products to market. However, some industry observers say this has led to buggy products, aberrant development practices, and stressed-out engineers.”

DATA MINING (p. 18) “… research groups, large businesses, government agencies, and other organizations are using improved mining technologies and techniques to discover meaningful patterns in huge databases. The technology is also looking for geological patterns in earthquake-prone areas, predicting bad credit risks, and anticipating inventory demands.”

DOMAIN NAMES (p. 22) “The small South Pacific island kingdom of Tonga is generating income and addressing the international shortage of domain names by selling domain names that include the country’s ‘.to’ generic top-level domain suffix.”

OPEN PAYMENT (p. 28) “Electronic funds transfer over financial networks is reasonably secure, but securing payments over open networks like the Internet poses challenges of a new dimension. This article surveys the state of the art in payment technologies and sketches emerging developments.”

PHYSICAL SCALABILITY (p. 37) “Many designers expect processor performance to keep improving at the current rate indefinitely as feature sizes shrink. However, as wire delays become a larger percentage of overall signal delay and as clock speeds grow faster than transistor speed, I believe performance increases will ultimately fall off.”

MEDIA APPLICATIONS (p. 43) “Media processing will force profound changes in current microprocessors. Yet general-purpose processors can and will adapt, making specialized digital signal processors for media applications essentially irrelevant.”

INTRODUCTION (p. 46) “Advances in semiconductor manufacturing will permit an unprecedented number of transistors on a single processor die. But what architecture will make the best use of these riches?”

PERFORMANCE (p. 51) “A billion transistors on a single chip presents opportunities for new levels of computing capability. Depending on your design point, several distinct implementations are possible. In our view, if the design point is performance, the implementation of choice is a very high-performance uniprocessor on each chip, with chips interconnected to form a shared memory multiprocessor.”

SUPERSPECULATION (p. 59) “Future billion-transistor chips will inevitably implement machines that are much wider (issue more than four instructions at once) and deeper (have longer pipelines). The question is, how do we harvest additional parallelism proportional to increased machine resources?”

UNIPROCESSOR (p. 68) “… there are primarily three ways to respond to this challenge: build a multiprocessor on chip, integrate more of the computer system on a chip, or build a large uniprocessor, which would realize the fourth generation of microarchitectures. We have chosen to explore building large uniprocessors, specifically trace processors.”

PROCESSOR+STORE (p. 75) “Conventional architectures will not efficiently scale a hundredfold to effectively utilize billion-transistor chips. A more efficient way of using the huge amount of real estate available is to integrate a high-performance processor and the DRAM main memory on the same die, an architecture called intelligent RAM, or IRAM.”

MULTIPROCESSOR (p. 79) “C[hip]MPs use relatively simple single-thread processor cores to exploit only moderate amounts of parallelism within any one thread, while executing multiple threads in parallel across multiple processor cores.”

MULTIMICROPROCESSOR (p. 86) “This innovative approach eliminates the traditional instruction set interface and instead exposes the details of a simple replicated architecture directly to the compiler. This allows the compiler to customize the hardware to each application.”

TECHNO MBAs (p. 129) “The computer industry can continue to create increasingly sophisticated hardware and applications. But if there’s no one to help implement them—translate them into terms businesses can understand and use—the market will never reach its full potential. It is this function that universities are training techno MBAs to fulfill and upon which the profits of computer companies rest.”

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