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Issue No.07 - July (2008 vol.41)

pp: 47-54

Kai-Hui Chang , University of Michigan, Ann Arbor

Igor L. Markov , University of Michigan, Ann Arbor

Valeria Bertacco , University of Michigan, Ann Arbor

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MC.2008.212

ABSTRACT

Due to increasing semiconductor design complexity, more errors are escaping presilicon verification and being discovered only after manufacturing. As an alternative to traditional manual chip repair, the authors propose the FogClear methodology, which automates the postsilicon debugging process and thereby reduces IC development time and costs.

INDEX TERMS

integrated circuits, electronic design automation, postsilicon debugging, validation, FogClear methodology

CITATION

Kai-Hui Chang, Igor L. Markov, Valeria Bertacco, "Automating Postsilicon Debugging and Repair",

*Computer*, vol.41, no. 7, pp. 47-54, July 2008, doi:10.1109/MC.2008.212REFERENCES

- 1. M. Abramovici et al., "A Reconfigurable Design-for-Debug Infrastructure for SoCs,"
Proc. 43rd Ann. Conf. Design Automation, ACM Press, 2006, pp. 7–12.- 2. R. Goering, "Post-Silicon Debugging Worth a Second Look,"
EE Times,5 Feb. 2007; www.eetimes.comshowArticle.jhtml?articleID=197002823 . - 3. K. Killpack, C.V. Kashyap, and E. Chiprout, "Silicon Speed-path Measurement and Feedback into EDA Flows,"
Proc. 44th Ann. Design Automation Conf., ACM Press, 2007, pp. 390–395.- 4. D.D. Josephson, "The Manic Depression of Microprocessor Debug,"
Proc. 2002 IEEE Int'l Test Conf., IEEE CS Press, 2002, pp. 657–663.- 5. K-H. Chang, I.L. Markov, and V. Bertacco, "Fixing Design Errors with Counterexamples and Resynthesis,"
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 1, 2008, pp. 184–188.- 6. K. Baker and J.V. Beers, "Shmoo Plotting: The Black Art of IC Testing,"
IEEE Design &Test of Computers, vol. 14, no. 3, 1997, pp. 90–97.- 7. H. Xiang et al., "An ECO Algorithm for Resolving OPC and Coupling Capacitance Violations,"
Proc. 6th Int'l Conf. ASIC, vol. 2, IEEE Press, 2005, pp. 873–876.- 8. K-H. Chang, I.L. Markov, and V. Bertacco, "Post-Placement Rewiring and Rebuffering by Exhaustive Search for Functional Symmetries,"
Proc. 2005 IEEE/ACM Int'l Conf. Computer-Aided Design, IEEE CS Press, 2005, pp. 56–63.- 9. K-H. Chang, I.L. Markov, and V. Bertacco, "Safe Delay Optimization for Physical Synthesis,"
Proc. 2007 Asia and South Pacific Design Automation Conf., IEEE CS Press, 2007, pp. 628–633.- 10. K-H. Chang, V. Bertacco, and I.L. Markov, "Simulation-Based Bug Trace Minimization with BMC-Based Refinement,"
IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 1, 2007, pp. 152–165.- 11. K-H. Chang, I.L. Markov, and V. Bertacco, "Reap What You Sow: Spare Cells for Postsilicon Metal Fix," to appear in
Proc. 2008 Int'l Symp. Physical Design, ACM Press, 2008.- 12. K-H. Chang, I.L. Markov, and V. Bertacco, "Automating Post-Silicon Debugging and Repair,"
Proc. 2007 IEEE/ACM Int'l Conf. Computer-Aided Design, IEEE Press, 2007, pp. 91–98. |