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Guest Editor's Introduction: Nanoscale Design & Test Challenges

Yervant , Virage Logic Corp.

Pages: pp. 36-39

Abstract—The silicon-scaling revolution presents a plethora of challenges as technology progresses into the nanoscale era. To meet these challenges, the design and test community has banded together to improve design automation and find solutions that will optimize performance at every level.

The silicon-scaling revolution is quite real and persistent. As we move to each new technology node, we attain a 50 percent area reduction and a 30 percent performance increase. The continuous scaling presents a plethora of design challenges as we progress into the nanoscale era, which imposes the need for additional design processes, such as design for manufacturability and power management, and introduces much higher mask and tooling costs.

Moreover, the bizarre vagaries of nanoscale technologies put a heavy burden on the test community, as scaling beyond 90 nanometers greatly extends process complexity and exacerbates leakage faults and soft errors. At the same time, process variants include new dielectrics, multiple oxide and metal layers, multiple voltage thresholds, and smaller noise margins, so that a product engineer faces serious yield implications.

The increasing number of available transistors is leading designers to incorporate even more on-chip functionality in the form of large embedded memories, base I/Os, and a variety of signal and protocol processing blocks. This is far outpacing designer productivity and is greatly increasing design complexity. Finally, with fabs expected to cost on the order of $3.5 billion and with skyrocketing reticle costs, successful companies must ship in high volumes with increased yields and amortize their design costs over multiple product lines by adopting, integrating, and reusing silicon-aware intellectual property blocks from qualified vendors.

To this end, the design community is working together to further design automation and improve design flows—be it silicon-aware IP design and delivery or hardware and software automation that lets designers work with higher-level languages and abstractions that hide the underlying process complexities and allow performance, power, and area optimization at every level. Similarly, the test community is looking beyond bolt-on test approaches to solutions such as infrastructure IP for embedded test, diagnosis, and repair. To maximize manufacturing yield, the infrastructure IP functions must be optimally tuned to the design under test.


To face these challenges, the design and test community has organized itself into several professional and business-oriented organizations. As the " Test Technology Technical Council" sidebar describes, the TTTC, a professional organization sponsored by the IEEE Computer Society, serves the worldwide test community with a wide range of activities, including educational programs, conferences, workshops, and standards.

The EDA Consortium is a business-oriented organization that represents 100 electronic design automation companies. The consortium seeks to identify and address issues that are common among these companies and the customer community they serve. By focusing on commonality and promoting cooperation, the consortium augments the effectiveness of design automation tools and services.

Established in 1994, the Fabless Semiconductor Association serves the design and test community by supporting the ongoing, symbiotic relationship between fabless semiconductor companies and their suppliers, including semiconductor foundries, IP providers, electronic design automation vendors, and design service houses. The FSA facilitates productive business partnerships, disseminates relevant data, and promotes the growth of the fabless business model.

These vibrant organizations are working together to address the many challenges that face the industry as we move to 90 nanometers and below. We are proud to be associated with Computer's Nanoscale Design & Test issue showcasing some of the exciting ideas that keep our industry ahead of Moore's law.


This issue features three articles describing various advanced aspects of design and test.

In "Robust System Design with Built-in Soft-Error Resilience," Subhasish Mitra and colleagues address the increasingly prevalent problem of soft errors or single-event upsets. Transient errors caused by terrestrial radiation pose a major barrier to robust system design, especially as chip sizes shrink and system susceptibility to error increases. The authors describe a number of soft-error protection techniques, including a strategy for using on-chip scan design-for-testability resources for soft-error protection during normal operation.

"Transistor-Level Optimization of Digital Designs with Flex Cells" by Rob Roy and colleagues explores another extremely important subject: the increasing need to reuse IP in today's chip designs. The use of precharacterized and silicon-verified standard cells is driven by the need to create and verify large digital circuits without having to verify the circuit's behavior at the transistor level, which is simply too resource intensive to be commercially viable for most designs. On the other hand, the quality of such automated standard-cell-based designs has been poor at best, running slower by a factor of 6 and consuming more area by a factor of 10. The quest to overcome these limitations leads naturally to the creation of new design- and context-specific cells—designated flex cells—during the process of optimizing a given digital design. Designers then use these cells via a combination of register-transfer-level coding style and synthesis directives.

Finally, the technical evolution we are witnessing today—particularly shrinking geometries—is enabling the integration of complex platforms in a single system on chip, and SoCs with more than 100 processors could become commonplace. Compared with conventional ASIC design, such a multiprocessor SoC requires a fundamental change in chip design. In "Hardware/Software Interface Codesign for Embedded Systems," Ahmed A. Jerraya and Wayne Wolf propose an interface-based HW/SW codesign methodology that takes advantage of IP blocks. Working at higher levels of abstraction, the productivity of a designer who can generate only 100 lines of Hardware Description Language code per day is higher if those lines represent large blocks rather than logic gates. The ultimate goal of this methodology is to design both hardware and software at all abstraction levels.


These three articles address only a limited subset of the challenges facing the design and test community. The community regularly conducts conferences, workshops, symposia, and forums offering opportunities to explore potential solutions to these challenges. As the accompanying sidebars describe, key examples of these opportunities include conferences like Design, Automation, and Test in Europe (DATE), cosponsored by the TTTC and EDAC; the International Test Conference (ITC) and VLSI Test Symposium (VTS), both cosponsored by the TTTC; publications such as IEEE Design & Test of Computers; and numerous standards, such as IEEE P1500. You are encouraged to further explore the exciting challenges in nanoscale design and test by participating in these events or by subscribing to D&T.

Test Technology Technical Council

The Test Technology Technical Council is a volunteer professional organization sponsored by the IEEE Computer Society. The TTTC's goals are to contribute to the professional advancement of the test community, help its members solve engineering problems in electronic test, and help advance the state of the art in test technology.

Through its more than 30 sponsored conferences and workshops, the TTTC serves as the primary source of knowledge about electronic test. Other TTTC efforts include its worldwide test technology educational program (TTEP); five geographically distributed regional groups; and a Web site, newsletter, and electronic broadcasts.

The TTTC is actively involved in identifying emerging topic areas in test technology. It initiates corresponding technical committees and nurtures the creation, adoption, and implementation of standards. Emerging topics that the TTTC currently covers include defect-based testing; debug and diagnosis; infrastructure IP; testing of FPGAs, memories, analog, and microprocessors; and test technology for embedded cores, boards, and system-on-chip, system-in-package, and electronic systems.

TTTC membership is open to all individuals directly or indirectly involved in test technology at a professional level. TTTC members pay no dues or fees.

To learn more about TTTC offerings and membership benefits, visit

Signature Conferences

Three signature conferences serve the global design and test community.




As the most comprehensive European conference and exhibition event, DATE brings together academic researchers, industry specialists, users, and vendors in the fields of design, automation, and test of electronic circuits and embedded systems.

The endless quest for faster, cheaper, and safer electronic products that consume less power—particularly for the growing consumer and communications markets—dictates generating increasingly complex designs in continually shrinking time scales. Design automation is a strategic technology for modern electronic systems, ranging from simple ASICs via embedded IP cores to large systems on chip made of heterogeneous processors communicating via on-chip networks. Testing these complex electronic systems is becoming a key factor in enabling the final quality goals, and it has an increasing impact on the overall cost of product development.

In addition to the regular paper sessions, DATE organizes interactive presentations for novel "ongoing work," offers a Designers' Forum devoted to the specific needs of designers, and provides a complete embedded software track.

DATE's educational day consists of tutorials and master courses. Five workshops follow the conference's conclusion. A PCB Symposium, fringe meetings, a University Booth, and social events during the conference offer a wide variety of opportunities to exchange information about relevant issues for the design, automation, and test communities. Special themes for DATE 05, scheduled for 7-11 March 2005 in Munich, are dedicated to automotive electronics and biochips.

The Executive Track, initiated for the first time in 2004, offers presentations by CEOs, CTOs, VPs, and other senior executives from EDA and semiconductor and system houses. Focusing on business and industry, a presentation theater located on the exhibition floor offers visitors and conference delegates a fresh view of economics, European strength in the industry, and challenges in the current electronic systems design market.




The world's premier conference dedicated to electronic test, ITC offers design and test professionals the opportunity to confront the challenges the industry faces and learn how academia, design tool and equipment suppliers, designers, and test engineers are combining their efforts to address these challenges.

As the cornerstone of Test Week, ITC offers a wide variety of technical activities targeted at test and design theoreticians and practitioners, including formal paper sessions, tutorials, panel sessions, case studies, lecture and application series, commercial exhibits and presentations, and a host of ancillary professional meetings. Some of the conference's most significant papers are now available online.

With the theme "Test: Survival of the Fittest," the 2005 conference will focus on evolving new "out-of-the-box" ideas to meet the tough test challenges presented by very-deep-submicron technologies and the competition for dominance among alternative solutions. ITC 2005 will be held 8-10 November in Austin, Texas;




The IEEE VLSI Test Symposium (VTS) explores emerging trends and novel concepts in testing, circuits, and systems. The three-day technical sessions respond to the many trends and challenges in the semiconductor design and manufacturing industries, featuring papers covering design validation, debug, test, repair, failure analysis, and fault tolerance for embedded IP cores, chips, boards, and systems.

In addition to the technical sessions, VTS features two keynote addresses, panels, embedded tutorials, hot topic sessions, and an Innovative Practices track. This track highlights the cutting-edge challenges that test practitioners face and explores the innovative solutions employed to address them.

The VTS program addresses a wide range of interests, including basic and continuing education for test professionals, the latest research developments, new directions and hot topics in test technology, and expert perspectives on current issues. Full-day tutorials and two full-day workshops are also held in conjunction with VTS. The tutorials are part of the Test Technology Education Program. In addition, VTS hosts a number of standardization Working Groups and IEEE Fringe Meetings. An exciting social program at VTS provides an opportunity for informal technical discussions among participants.

VTS is sponsored by the TTTC and will take place 1-5 May 2005 in Palm Springs, Calif.;

IEEE P1500 Standard for Embedded Core Test

The IEEE Computer Society's Test Technology Technical Council initiated IEEE P1500 Standard for Embedded Core Test (SECT) in 1995 as a Technical Activities Committee to identify the common needs in the system-on-chip test domain. In 1997, the IEEE Standards Board granted permission to start the IEEE P1500 standards activity. In January 2005, IEEE P1500 went through a successful recirculation.

Since its inception, P1500 has focused on the critical aspects of ease of reuse and interoperability with respect to testing when IP cores originating from distinct core providers come together in one SoC. P1500 standardizes core test information, model transfer, and test access for embedded cores, concentrating on areas that are at the interface between core provider and core user. As a scalable standard, IEEE P1500 contributes to ease of plug-and-play for testing, while maintaining the required flexibility to cope with different cores and system chips.

Leading volunteer experts in relevant industry segments, such as systems companies, EDA vendors, core providers, IC manufacturers, and automated test equipment suppliers, have actively participated in developing IEEE P1500. The first version of the standard focuses on nonmerged digital logic and memory cores. In future extensions, P1500 will cover analog and mixed-signal cores, as well as the design-for-test guidelines for mergeable cores.

The two main elements of the IEEE P1500 standard are a scalable core test architecture and an information model. For the scalable architecture, P1500 does not standardize test pattern sources, sinks, or test access mechanisms—that is, the test access "highway" from source to core to sink. With respect to test access for embedded cores, P1500 only standardizes the test wrapper around the core and its interface to one or more test access mechanisms. The information model is meant to standardize the core test knowledge transfer. The P1500 information model is based on IEEE P1450.6, a standard initiated to accommodate specific core test constructs. The IEEE P1450.6 Working Group collaborates to provide the necessary language for P1500 core test knowledge transfer.

For additional information about this hot topic, visit the P1500 Web site:

IEEE Design & Test of Computers

IEEE D&T, a bimonthly magazine copublished by the IEEE Computer Society and the IEEE Circuits and Systems Society, is specifically directed to design and test engineers and researchers. D&T features peer-reviewed original work describing methods and practices used to design and test electronic product hardware and supportive software as well as design automation tools and methodologies.

D&T publishes tutorials, perspectives, roundtable discussions, viewpoints, conference reports, panel summaries, and standards updates contributed by authors working in the industry.

Paper submission: Submit manuscripts for peer review to D&T at Each submitted paper undergoes at least three technical reviews. All submissions must be original, previously unpublished work. The theme issues for 2005 are Design & Test Methodologies for Scaled Technologies, Configurable Computing, Design for Manufacturability, Nanotechnology, Multiprocessor SoCs and Networks on Chip, and 3D Integration.

Subscription: IEEE D&T offers full-year and half-year subscriptions for print issues. In addition, it offers electronic subscription options to IEEE CS and CAS members, with full-text searchable access to all issues from 1995 forward.

Visit D&T's Web page to access tables of content and article abstracts online at no cost:

About the Authors

Yervant Zorian is vice president and chief scientist of Virage Logic. He received an MSc in computer engineering from the University of Southern California and a PhD in electrical engineering from McGill University. Zorian also received an executive MBA from the Wharton School of the University of Pennsylvania. He is an IEEE Fellow, serves as IEEE Computer Society Vice President for Conferences & Tutorials, and is the editor in chief emeritus of IEEE Design & Test of Computers. Contact him at
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