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The Internet is not meeting its potential for delivering geographically oriented information. Sometimes the information people seek is on the Internet, but the tools for locating it are inadequate. In other cases, our industry has not developed the counterparts needed to replace traditional delivery methods such as the printed Yellow Pages.
The Internet Yellow Pages, currently the main source of local content on the Internet, are reliable, but they are also shallow, slow to change, centralized, and expensive. Their primary data sources are printed telephone directories. They do not use the Internet's resources in any meaningful way.
Geosearch, a geoenabled search engine that lets people search for Web pages that contain geographic markers within a specified geographic area, demonstrates that the Internet is a rich source of local content. It also demonstrates the many advantages that postal addresses have as a key for accessing this content, especially when the content pertains to the activities of daily life.
Subhasish Mitra, Norbert Seifert, Ming Zhang, Quan Shi, and Kee Sup Kim
Soft errors, also called single-event upsets, are radiation-induced transient errors caused by neutrons generated from cosmic rays and alpha particles generated by packaging material. Traditionally, soft errors were regarded as a major concern only for space applications. Yet, for designs manufactured at advanced technology nodes—such as 90 nm or 65 nm—system-level soft errors occur more frequently than in previous generations.
Chip designers must address soft errors very early, starting from the product definition phase and continuing through the architecture planning, circuit design, logic design, and postlayout phases. The effects of soft errors in sequential elements such as flip-flops, latches, and combinational logic must be evaluated, and effective protection mechanisms incorporated into the design.
Rob Roy, Debashis Bhattacharya, and Vamsi Boppana
Over the years, it has become commonplace to perform various forms of manual intervention on designs generated using automated flows. The quest to overcome the limitations of standard-cell-based design methods leads naturally to the creation of new design- and context-specific cells—designated flex cells—during the process of optimizing a given digital design. Flex-cell-based design optimization automates the creation of tactical cells.
The flex-cell approach, either alone or in combination with standard cells, provides an optimally tuned set of building blocks for the target IC design, which measures optimality against accepted and quantifiably definable metrics such as clock speed, die size, and power consumption. By allowing manipulation of the transistor-level structures, flex cells open up a new dimension in the optimization of automatically created designs.
Ahmed A. Jerraya and Wayne Wolf
Technological evolution—particularly shrinking silicon fabrication geometries—is enabling the integration of complex platforms in a single system on chip. In addition to specific hardware subsystems, a modern SoC also can include one or several CPU subsystems to execute software and sophisticated interconnects.
Mastering the design of these embedded systems challenges both the system and semiconductor houses that used to apply a software- or hardware-only strategy. In addition to classic software and hardware, SoC engineers must design hardware-dependent software and software-dependent hardware. Codesigning these HW/SW interfaces requires a new kind of engineer who understands both hardware and software design.
Providing SoCs consisting of an assembly of processors executing tasks concurrently will require design methodologies to focus on selecting and using either programmable or dedicated processors in place of the gates and arithmetic logic units that current methods use.
Claudio Talarico, Jerzy W. Rozenblit, Vinod Malhotra, and Albert Stritter
Among the many metrics used to characterize the quality of an embedded system-on-chip design, power consumption has emerged as one of the most important. This is largely due to the proliferation of mobile battery-powered computing devices, the increasing speed and density of CMOS (complementary metal-oxide semiconductor) VLSI (very large-scale integration) circuits, and continuous shrinking of the transistor feature size of deep-submicron technologies.
The authors have developed a technique that derives power figures from the execution of high-level models. This technique makes it possible to assess embedded SoC designs much earlier in the design cycle, contributing to sounder decisions throughout the entire development process and leading to a faster execution time. To validate their methodology, the authors applied it to a peripheral core—a baud rate generator—and compared the results with those obtained using a gate-level approach.