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Issue No. 10 - October (2002 vol. 35)
ISSN: 0018-9162
pp: 63-68
Samitha Samaranayake , Massachusetts Institute of Technology
Nodari Sitchinava , Massachusetts Institute of Technology
Rohit Kapur , Synopsys
Minesh B. Amin , Synopsys
<p>Two factors primarily drive the soaringcost of semiconductor test: thenumber of test patterns applied toeach chip and the time it takes to runeach pattern. Typical semiconductortesting for each chip involves a set of1,000 to 5,000 test patterns. These testsare applied through scan chains thatoperate at about 25 MHz. Depending onthe size of the scan chains on the chip, aset of test patterns can take a few secondsto execute per chip.</p><p>It?s easy to see that even a smalldecrease in either the number of patternsor the time to execute them can quicklyadd up to big savings across millions offabricated chips. This potential savingsforms the basis for dynamic scan, a newapproach to the well-established scan testmethodology.</p><p>The authors? initial studies indicate thatdynamic scan could easily reduce the timespent applying test patterns by 40 percent.A more theoretical analysis shows apotential savings of as much as 80 percent.</p>

M. B. Amin, N. Sitchinava, R. Kapur, S. Samaranayake and T. W. Williams, "Dynamic Scan: Driving Down the Cost of Test," in Computer, vol. 35, no. , pp. 63-68, 2002.
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