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<p>The early 1990s saw several announcements of commercial shared-memory systems using processors that aggressively exploited instruction-level parallelism (ILP), including the MIPS R10000, Hewlett-Packard PA8000, and Intel Pentium Pro. These processors could potentially reduce memory read stalls by over-lapping read latency with other operations, possibly changing the nature of performance bottlenecks in the system.</p><p>The authors' experience with Rsim demonstrates that modeling ILP features is important even in shared-memory multiprocessor systems. In particular, current simple processor-based approximations cannot model significant performance effects for applications exhibiting parallel read misses. Further, recent shared-memory designs such as aggressive implementations of sequential consistency use the aggressive ILP-enhancing features of modern processors that simple processor-based simulators do not model.</p><p>As microprocessor systems become more complex, the availability of shared infrastructure source code is likely to become increasingly crucial. The authors plan to release a new Rsim version shortly that will include instruction caches, TLBs, multimedia extensions, simultaneous multithreading, Rabbit fast simulation mode, and ports to Linux platforms.</p>
Sarita V. Adve, Parthasarathy Ranganathan, Vijay S. Pai, Christopher J. Hughes, "RSIM: Simulating Shared-Memory Multiprocessors with ILP Processors", Computer, vol. 35, no. , pp. 40-49, February 2002, doi:10.1109/2.982915
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