Issue No. 12 - December (2000 vol. 33)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/2.889095
<p>Rapid increases in processor speed and slower increases in memory speed have produced memory access times that exceed the cost of simple, arithmetic operations. The ubiquitous hardware solution to this problem is memory caches, which exploit program locality to reduce the average latency. Other techniques use complex hardware and software to reduce or hide the high cost of memory accesses.</p> <p>The processor-memory gap requires a hierarchy of two or more caches between the processor and memory. The cost of finding data in this hierarchy undercuts the fundamental RAM model assumption that all memory accesses have unit cost.</p> <p>To narrow the widening gap between processor and memory performance, the authors propose using pointer structures to bolster performance by placing elements in a compound data structure in different memory and cache locations. This careful placement of structure elements enhances the performance of pointer-minipulating programs by improving their cache locality.</p>
M. D. Hill, J. R. Larus and T. M. Chilimbi, "Making Pointer-Based Data Structures Cache Conscious," in Computer, vol. 33, no. , pp. 67-74, 2000.