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Issue No. 11 - November (1999 vol. 32)
ISSN: 0018-9162
pp: 66-74
<p>The customer expects defect-free chips, even at consumer prices-making thorough manufacturing test mandatory. With increasing chip density, the addition of say 10,000 gates is no longer of great impact (these would occupy only 0.1 mm2 on a die); satisfying timing requirements and not exceeding package or system power requirements are the principal implementation objectives. The new availability of silicon real estate has transformed the design-for- testability environment. Implementing contemporary application-specific integrated circuit (ASIC) designs based on standard-cell and gate array technologies now requires design flows that incorporate DFT. Robust design for testability in very deep-submicron (VDSM) technologies is essential to volume manufacturing. The most common structural test method is scan-based logic test, which is now the backbone of manufacturing test. Using this method, commercial ATPG tools rely on test-mode reconfiguration of the circuit to a pseudo-combinational one, ensuring its access, controllability, and observability. Each state bit is trans-formed into a stage (either a flip-flop or master-slave latch pair) of a shift register or scan chain accessible from chip pins. The author points out ways to avoid pitfalls in implementing effect scan-based test. These include modifying register-transfer- level circuit representations for testability, using single clock edge design, and providing clock control.</p>
Kenneth D. Wagner, "Robust Scan-Based Logic Test in VDSM Technologies", Computer, vol. 32, no. , pp. 66-74, November 1999, doi:10.1109/2.803644
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