Issue No. 11 - November (1999 vol. 32)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/2.803640
<p>The introduction of nanometer technologies into the imperfect manufacturing process of ICs presents new challenges for identifying defects that creep into some fabricated chips. Defects are unpredictable in both location and effect, and the processes that cause them include a wide range of variables. These defects can take a variety of forms, from localized spot defects-typically extra or missing material caused by particles-to defects affecting much larger areas, such as reduced capacitance caused by inadequate implantation. To simplify the identification of defective circuits, this infinite defect space is approximated by a finite set of faults. Faults are deterministic, discrete changes in circuit behavior. They are often considered localized within a circuit (for example, when a particular gate is broken) and can also be thought of as transformations that change the Boolean function implemented by a circuit. Research into fault models has generated new methods for extending them from the gate level to the presynthesized register-transfer-level (RTL) and behavioral code. Chip designers can use simple models-such as stuck-at faults-to find a wide variety of defects. Nanometer technologies will require innovative delay fault models and techniques to extend the life of test methods like IDDQ.</p>
R. C. Aitken, "Nanometer Technology Effects on Fault Models for IC Testing," in Computer, vol. 32, no. , pp. 46-51, 1999.