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Issue No. 11 - November (1999 vol. 32)
ISSN: 0018-9162
pp: 25-33
<p>Several independent sources forecast that in deep-submicron (DSM) process geometries, 80 percent or more of the delays of critical paths will be directly linked to interconnect. This forecast is supported by the significant timing-closure problems that are arising in current high-performance IC designs. Based on this, both industry and academia sense the need for a significant over-haul of current synthesis and physical-design methodologies. In the emerging design scenario, traditional design flows will no longer be viable for any size of module or block of gates. Deep-submicron effects-particularly those relating to interconnects-have thus been billed as potential roadblocks to the continuation of Moore's law. Some effects, like the rising resistance-capacitance (RC) delay of on-chip wiring, noise considerations, reliability concerns, and increased power dissipation, manifest themselves in both the devices (transistors) and the interconnect, though not in ways previously anticipated. The authors consider the effects of both devices and interconnect. Their analysis shows that interconnect delay actually decreases for DSM processes in a modular design approach. The physical explanations of these DSM effects shed insight into this and other potential impacts on future high-performance ASIC designs.</p>

D. Sylvester and K. Keutzer, "Rethinking Deep-Submicron Circuit Design," in Computer, vol. 32, no. , pp. 25-33, 1999.
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