Issue No. 07 - July (1998 vol. 31)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/2.689674
Over the past several years, strategies to increase microprocessor performance have focused on finding more instruction-level parallelism. ILP is basically the idea of finding several instructions to execute at the same time. By providing multiple functional units on which to execute instructions, computer architects expect to improve performance. However, two difficult problems limit ILP: branch instructions, which introduce control dependencies, and memory latency, the time it takes to retrieve data from memory. In the absence of new programming languages that are explicitly parallel, the task of "exposing" ILP falls to the compiler. In IA-64, Intel's upcoming 64-bit architecture, the compiler will play a pivotal role in using predication and control speculation to expose more ILP. To illustrate predication and control speculation, this article presents two code fragments scheduled with actual IA-64 instructions that are representative of general-purpose integer code, such as that found in computer-aided design and database applications. A comparison of performance with and without the two features demonstrates how predication and control speculation can yield a significant reduction in the number of cycles required to execute an instruction.
Carole Dulong, "The IA-64 Architecture at Work", Computer, vol. 31, no. , pp. 24-32, July 1998, doi:10.1109/2.689674