Issue No. 09 - September (1997 vol. 30)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/2.612245
<p>The most important physical trend facing chip architects is the fact that on-chip wires are becoming much slower relative to logic as the on-chip devices shrink. The author points out that it will soon be impossible to maintain one global clock over the entire chip, and sending signals across a billion-transistor processor may require as many as 20 cycles. </p>
D. Matzke, "Will Physical Scalability Sabotage Performance Gains?," in Computer, vol. 30, no. , pp. 37-39, 1997.